Modelling of Tunnelling Currents in Metal-Insulator-Metal Junction
Ajay Manwani, Rajesh Junghare and Abhishek Vaidya, Visvesvarya National Institute of Technology, India
Design and Analysis of High Gain Cmos Telescopic OTA in 180nm Technology for Biomedical ind RF Applications Sarin V Mythry, P. Nitheesha Reddy, Syed Riyazuddin, T. Snehitha and M. Shamili, Christu Jyothi Institute of Technology and science, India
A Novel CMOS Dynamic Latch Comparator for Low Power and High Speed Shilpi Singh, Indira Gandhi Technical University for Women, India
Power Factor Measurement and Correction using Digital Controller Implemented on FPGA ArindamBiswas, SujitDhar, Ashoke Kumar Basu and AmarnathSanya, Neotia Institute of Technology, West Bengal
Performance Analysis Of Low Power Full Adder Cells Using 45nm Cmos Technology K.Dhanunjaya1, MN.Giri Prasad2 and K.Padmaraju3, 1JNTUA Anatpuramu, India, 2JNTUA, India and 3JNTUK, India
Genetic Algorithm for Leakage Reduction Through IVC Using Verilog S.Meera and D.Umamaheswari, EBET Group of Institutions, India
