Accepted Papers

  • Simultaneous Localization and Mapping (SLAM) of an Autonomous Robot by Sonar range sensing.
    Trishala Sherigara, SJB Institute of Technology, India
    SLAM stands for simultaneous localization andarea mapping. It deals with mapping areas which are uncharted or are not easily accessible in a given environment as well as updating currently available maps, while at the same time keeping track of the current location using the map generated. This is often used with autonomous robots and unmanned vehicles, to map hostile or unfriendly or unknown environments. Commonly used SLAM hardware is very expensive. This work deals with optimizing economic constraints and quality with minimum trade-off between the two. This is done using open source software and limited number of sensors, which makes the prototype very easy to implement. It also uses a very easy, straight forward algorithm to map the surroundings using sonar.
  • Performance Analysis of Six Legged Robotic System for Disaster Rescue
    S.Senthilkumar 1, P.Suresh2
    1Mahendra Engineering College, Namakkal Tamilnadu, India 2 Karpagam College of Engineering, Coimbatore, Tamilnadu, India
    This paper exhibits the hexapod robot movement performance.The Hexapod robot movement analysis was made using Virtual Robot Experimentation Platform (V REP) software. Through this simulation we can analysis the performance of hexapod robot body and legs movement in various parameters. The Robotic system was separately analyzed and the simulation results are given. This types of robots are used in rescue purpose to find the people using the sensors and cameras.
  • Design of High-Q Mems Filter
    Supriya kamble 1, V.R Rathee2
    Over the past few years, significant growth has been observed in using MEMS based passive components especially in RF transceiver. This is due to some excellent properties of the MEMS devices like low loss, low cost, excellent isolation etc. This paper present design of high performance MEMS passive butterworth low pass filter, consisting of parallel plate capacitor and the planar spiral inductors. This paper also present design ,simulation and analysis of mems passive filter along with the comparative study between different order of the filter .This filters were designed to have a cutoff frequency of 1GHz, meant for a use of the telecommunication transreceiver in Bluetooth, military application. Some of the filters parameters like quality factor, size, insertion loss are optimized. This paper also presents the design and analysis of high-performance mems inductor.
  • Analysis of 3- and 5-Level Inverters Based SVPWM for power quality purpose
    Ahmed Sanabary 1,Ahmed Kalas2
    Portsaid University,Egypt
    Multilevel inverter technology has become the most important solution for high-power medium-voltage power transmissions and drives. This paper includes a comparative analysis of the performance of 3-level and 5-level inverters connected to induction motor for power quality purposes. A space vector modulation algorithm is applied for this comparison. It's likely to show the benefits of increasing the number of levels in an inverter. This algorithm is applicable to NPC and cascaded topologies. In order to reduce the total harmonic distortion of the resulted voltage waveform a passive filter is carefully designed. In this paper, simulation results are carried out using Matlab/Simulink software environment.
  • 4 Bit Arithmetic and Logical Unit (ALU) on FPGA Using Vedic Math
    Trishala Sherigara,SJB INSTITUTE OF TECHNOLOGY,India
    Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Minimizing power consumption for digital systems involves optimization at all levels of the design. In this, Urdhva Tiryakbhyam Sutra is first applied to the binary number system and is used to develop digital multiplier architecture. This is shown to be very similar to the popular array multiplier architecture. The main objective of this is to design and implementation of a fast multiplier with self testing, which can be used in any processor application. Architecture of Vedic multiplier based on speed specification is designed here. Hardware Implementation of this multiplier has been done on Spartan 3 board and then implemented on FPGA.
  • Finite Element Analysis of PCB multilayer stack up for High voltage planar transformer
    Kiran Gaikwad ,India
    High Voltage, high power planar magnetic devices are becoming a replacement to their conventional rivals due to their higher reliability, better reproducibility and higher efficiency. Also this printed circuit replaces typically wire wound coils to flat, extremely durable, high temperature resilient and high inner layer, voltage dielectric breakdown rating PCB tracks. This paper includes, study and solution methods for PCB winding configuration in planar magnetic elements with multilayer stack up of PCB Cu-tracks instead of traditional windings producing High Voltage power supply for aerospace application. With Finite Element Analysis (FEA) simulations, different simulation outcomes are discussed for inspecting Flux intensity and current density distribution with computing Electric field strength and Magnetic fields. In principal conclusion of study, complete analysis and some practical design guidelines of multilayer PCB stack up and their feed through are discussed in this paper.
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