Scope & Topics

International Journal of Electronic Design and Test(JEDT) is a peer-reviewed, open access journal which invites original works describing the methods used to design and test electronic product hardware and supportive software. Authors from industry and academia are invited to submit their original unpublished research works on the topics listed below:

Topics of interest include but are not limited to, the following

  • IC/module design
  • Low-power design
  • Electronic design automation
  • Design/test verification
  • Fault modelling
  • Test generation
  • Fault simulation
  • Design of testability
  • Synthesis of testability
  • Built-in self-test
  • Test specifications
  • Formal verification of hardware
  • Simulation for verification
  • Design debugging
  • Testing of VLSI devices printed circuit boards, and electronic systems
  • Testing of analog and digital electronic circuits
  • Testing of microprocessors, memories and signal processing devices
  • SOC and SIP testing
  • Memory and FPGA test and repair
  • Delay testing
  • IDDQ test
  • Novel test methods
  • Effectiveness of test methods
  • Fault models and ATPG, and DPPM prediction
  • DFT for analog/mixed signal ICs and system-on-chip
  • DFT and BIST for digital and SoC

Important Dates

  • Submission Deadline : May 14, 2025
  • Notification                   : June 16, 2025
  • Final Manuscript Due : June 23, 2025
  • Publication Date          : Determined by the Editor-in-Chief

Call for Papers